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Design of Systems on a Chip: Design and Test
Design of Systems on a Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
Kindle Edition
First published October 3, 2006
About the author
Ricardo Reis
86 books35 followersA heteronym of Fernando Pessoa.
"Around 1912, if I’m not mistaken (not greatly anyway), the idea came to me to write poems of a pagan nature. So I scribbled something down in irregular verse (different to the style of Álvaro de Campos, more irregular), and abandoned the idea. It was a badly woven twilight, a blurred portrait of the person who was composing it. (I hadn’t realized it yet, but that was when Ricardo Reis was born)."
Fernando Pessoa writes in his letter dated Janeiro 13th 1935 to Adolfo Casais Monteiro, that Ricardo Reis was born in 1887 (although he couldn’t recall the exact date), in Oporto. He describes him as shorter, stronger and stiffer than Caeiro, besides being clean shaven. He had had a Jesuit school education, was a doctor and had lived in Brazil since 1919, from where he had been self-expatriated for being a supporter of the monarchy. He had Latin and semi-Hellenic instruction.
Fernando Pessoa admits he conferred to this heteronym and excessive purity and writing as Ricardo Reis mentions he "followed an abstract deliberation which immediately took the shape of an ode".
Source: Fernando Pessoa's Letter to Adolfo Casais Monteiro, January 13th 1935, in Correspondência 1923-1935, ed. Manuela Parreira da Silva, Lisbon Assírio & Alvim, 1999.
"Around 1912, if I’m not mistaken (not greatly anyway), the idea came to me to write poems of a pagan nature. So I scribbled something down in irregular verse (different to the style of Álvaro de Campos, more irregular), and abandoned the idea. It was a badly woven twilight, a blurred portrait of the person who was composing it. (I hadn’t realized it yet, but that was when Ricardo Reis was born)."
Fernando Pessoa writes in his letter dated Janeiro 13th 1935 to Adolfo Casais Monteiro, that Ricardo Reis was born in 1887 (although he couldn’t recall the exact date), in Oporto. He describes him as shorter, stronger and stiffer than Caeiro, besides being clean shaven. He had had a Jesuit school education, was a doctor and had lived in Brazil since 1919, from where he had been self-expatriated for being a supporter of the monarchy. He had Latin and semi-Hellenic instruction.
Fernando Pessoa admits he conferred to this heteronym and excessive purity and writing as Ricardo Reis mentions he "followed an abstract deliberation which immediately took the shape of an ode".
Source: Fernando Pessoa's Letter to Adolfo Casais Monteiro, January 13th 1935, in Correspondência 1923-1935, ed. Manuela Parreira da Silva, Lisbon Assírio & Alvim, 1999.
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